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- Timestamp:
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Jun 16, 2010, 3:36:54 PM (14 years ago)
- Author:
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khanhle
- Comment:
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--
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v11
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v12
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37 | 37 | * '''Timing Control''' - system wide clock control using clock enables [[BR]] |
38 | 38 | |
39 | | From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier forwards RMAP specific frames to RMAP Processor, whereas data specific frames are routed to the Data processing functions. RMAP frames are parsed by the RMAP processor, where a register map read/write operation can be initiated. |
| 39 | From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier classifies and forwards packets according to its |
| 40 | type : |
| 41 | * RMAP packets -> RMAP Processor |
| 42 | * Data packets -> Tx Buffer for APP processing |
| 43 | * Other packets -> TCP/IP stack |
40 | 44 | |
41 | 45 | For RMAP read operations, read data must be forwarded back to Host. This is accomplished by following operations : [[BR]] |
42 | | 1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.[[BR]] |
43 | | 2. Generate IP and Ethernet frame for transmission back to host. Some control header information are added in the |
44 | | payload section for Host RMAP read synchronization.[[BR]][[BR]] |
| 46 | 1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.[[BR]] |
| 47 | 2. Generate IP and Ethernet frame for transmission back to host. Some control header information are added in the payload section for Host RMAP read synchronization.[[BR]][[BR]] |
45 | 48 | |
46 | 49 | === Global Memory Map === |