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Changes between Version 3 and Version 4 of Software/Firmware/Framework/R3_arch/outline/blk_spec/app/rx/f1


Ignore:
Timestamp:
Jul 16, 2010, 3:38:57 AM (14 years ago)
Author:
khanhle
Comment:

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  • Software/Firmware/Framework/R3_arch/outline/blk_spec/app/rx/f1

    v3 v4  
    66[[BR]][[BR]]
    77
    8 R3 architecture consists of following modules :
     8Architecture summary :
    99
    10  * '''Ethernet Port''' - Ethernet framing function, [[BR]]
    11     * Rx - receives ethernet frames from Host. Performs CRC checking, and forwards error free payload to packet processor.
    12     * Tx - transmits ethernet frames to Host. Generates Ethernet header and CRC, IP payload is provided by packet processor.  [[BR]]
     10 * '''Data Load''' - Fetch I/Q data sync fifo, forward to FFT Core [[BR]]
     11 
     12 * '''FFT''' - Compute Fast Fourier Transform [[BR]]
     13    * FFT Core - Programmable number of FFT points e.g. N = 8, 16, 32, 64, 128, 256, 512 or 1024-pt
     14    * FFT Ctl  - Initiate start of FFT processing, can be used to throttle the FFT packet rate
    1315
    14  * '''Packet Processor''' - IP layer processing[[BR]]
    15     * Packet classification - RMAP, Data, and other (such as ARP and DHCP packets)
    16     * UDP is used for board level communication e.g. RMAP and Data packets
     16 * '''Average/Power''' - Compute Power average using incoming FFT I/Q data[[BR]]
     17    * AVG Processor - Compute power using previous data (stored in AVG RAM) and current data from FFT Core
     18    * AVG Prefetch  - Fetch previous computed average data and forward to AVG Processor. At the end of average processing, forward payload to Packet Processor for IP/UDP wrapping.   
     19    * AVG Control   - Initiate start of Averaging/Power calculation, N''avg'' = 2, 4, 6, 8, 16, 32, 64, 128, 256
    1720
    18  * '''APP''' - User specific application [[BR]]
    19    
    20  * '''RF Port''' - DAC/ADC interfacing [[BR]]
    2121
    22  * '''Control Plane''' - RMAP and RF control [[BR]]
    23 
    24  * '''Timing Control''' - system wide clock control using clock enables [[BR]]
    25 
    26 From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier classifies and forwards packets according to its
    27 type :
    28  * RMAP packets  -> RMAP Processor
    29  * Data packets  -> Tx Buffer for APP processing
    30  * Other packets -> TCP/IP stack
    3122
    3223[..]