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Version 3 (modified by khanhle, 14 years ago) ( diff )


RMAP Processor

Figure 1 - RMAP Processor IO

Table 1 - Tx Command Generator Interface

Signal NameIn/OutWidthDescription
sofIn1Start of frame signal
eof In1 End of frame signal
dataIn32input data
wr_enIn1data enable signal
full_flagOut1rmap fifo full flag

Table 2 - RMAP Interface

Signal NameIn/OutWidthDescription
addr Out 32 RMAP address signals
data Out 32 RMAP data signals
cs Out 1 chip select, active high when RMAP is being accessed
rnw Out 1 Read/Write, '1' - Read, '0' - Write
rd_ack In 1 Read ack signal, signals end of read cycle e.g. sample read data
wr_ack In 1 Write ack signal, signals end of write cycle
rd_data In 32 read data, in sync with rd_ack
intr In 1 Interrupt, this signal is edge-detected inside RMAP processor

Table 3 - Rx Memory Control interface

Signal NameIn/OutWidthDescription
req Out 1request signal, hold until ack
ack In 1ack from Rx memory control, single clock pulse
sof Out 1 start of frame,
eof Out 1 end of frame
data Out 32data
1st word - type field e.g. 0x2000 for generic data, 0x2001 for interrupt (sof == 1)
2nd word - rmap address field
3rd word - rmap read data field (eof == 1)
data_en Out 1 data enable, high when data is valid


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