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Changes between Version 4 and Version 5 of Software/Firmware/Framework/R3_arch/outline/mem_map


Ignore:
Timestamp:
Jun 29, 2010, 8:24:53 PM (12 years ago)
Author:
khanhle
Comment:

--

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  • Software/Firmware/Framework/R3_arch/outline/mem_map

    v4 v5  
    99||''Reserved''        ||0x00000000-0x0FFFFFFC||-        ||Future use||
    1010||''[source:/doc/trunk/architecture/rmap/R3/cplane_cmn_rmap.xls Common Control]''  ||0x10000000-0x1000FFFC||65K      ||Control Plane register map e.g. SPI, LEDs, and board level IO||
    11 ||''Common INTC''     ||0x10010000-0x1001FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
     11||''[source:/doc/trunk/architecture/rmap/R3/cplane_intc_rmap.xls Common INTC]''     ||0x10010000-0x1001FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
    1212||''Timing Control''  ||0x10020000-0x1002FFFC||65K      ||address range for timing controller||
    1313||''Ethernet Port''   ||0x10030000-0x1003FFFC||65K      ||address range for Tx and Rx Ethernet ports||