== Memory Map ==

R3 global memory map is divided into multiple regions as shown in Table 1. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bit31-28 are used for region address decoding between the individual regions as illustrated in Figure 1. Each address range gets its own chip select. 

For detailed definition for each RMAP, click on provided links under ''Instance'' column in Table 1. Note that the RMAP addresses are given as offsets, and must be added to Base address to get the correct address pointer to RMAP register. Example - Common Control base address == 0x10000000, hence Common Control RMAP real address == RMAP offset + 0x10000000 (base).   

__Table 1 - R3 Global Memory Map__
||'''Instance'''      ||'''Address Range'''||'''Size'''  ||'''Description'''||
||''Reserved''        ||0x00000000-0x0FFFFFFC||-        ||Future use||
||''[source:/doc/trunk/architecture/rmap/R3/cplane_cmn_rmap.xls Common Control]''  ||0x10000000-0x1000FFFC||65K      ||Control Plane register map e.g. SPI, LEDs, and board level IO||
||''[source:/doc/trunk/architecture/rmap/R3/cplane_intc_rmap.xls Common INTC]''     ||0x10010000-0x1001FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
||''Timing Control''  ||0x10020000-0x1002FFFC||65K      ||address range for timing controller||
||''Ethernet Port''   ||0x10030000-0x1003FFFC||65K      ||address range for Tx and Rx Ethernet ports||
||''Packet Processor''||0x10040000-0x1004FFFC||65K      ||address range for packet processor||
||''[wiki:Software/Firmware/Framework/R3_arch/outline/mem_map/app_tx Tx APP]''          ||0x10050000-0x1005FFFC||65K      ||address range for Tx Application||
||''[wiki:Software/Firmware/Framework/R3_arch/outline/mem_map/app_rx Rx APP]''          ||0x10060000-0x1006FFFC||65K      ||address range for Rx Application||
||''RF Port - DAC''   ||0x10070000-0x1007FFFC||65K      ||address range for DAC interfacing module||
||''RF Port - ADC''   ||0x10080000-0x1008FFFC||65K      ||address range for ADC interfacing module||
||''Reserved''        ||0x10090000-0xFFFFFFFC||-        ||Future use||
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__Figure 1 - R3 Address Decoding__ 
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[[Image(r3_addr_dec.jpg)]]
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