| | 3 | With R3, we have included a dedicated control plane with RMAP processor which will handle all register map |
| | 4 | related accesses. In future releases, we may replace the RMAP processor with a real 32-bit soft processor such |
| | 5 | as Xilinx Microblaze, or equivalent processors. |
| | 6 | |
| | 7 | The register maps associated with the control plane handle all Board related controls e.g. RF SPI, general purpose |
| | 8 | IOs, LEDs and so forth. Whereas, data plane centric register maps are maintained within the Tx and Rx Application modules. |
| | 9 | Within the APP module, we have an option of having a top level RMAP, and/or an application specific RMAP. Usually, the top |
| | 10 | level RMAP is shared among multiple applications, whereas application specific RMAPs are only designed for a particular application. |
| | 11 | |
| | 12 | __Figure 1 - R3 architecture overview__ |
| | 13 | [[BR]][[BR]] |
| | 14 | [[Image(r3_arch.jpg, 1200px)]] |
| | 15 | [[BR]][[BR]] |
| | 16 | |
| | 17 | R3 architecture consists of following modules : |
| | 18 | |
| | 19 | * '''Ethernet Port''' - Ethernet framing function, [[BR]] |
| | 20 | * Rx - receives ethernet frames from Host. Performs CRC checking, and forwards error free payload to packet processor. |
| | 21 | * Tx - transmits ethernet frames to Host. Generates Ethernet header and CRC, IP payload is provided by packet processor. [[BR]] |
| | 22 | |
| | 23 | * '''Packet Processor''' - IP layer processing[[BR]] |
| | 24 | * Packet classification - RMAP, Data, and other (such as ARP and DHCP packets) |
| | 25 | * UDP is used for board level communication e.g. RMAP and Data packets |
| | 26 | |
| | 27 | * '''APP''' - User specific application [[BR]] |
| | 28 | |
| | 29 | * '''RF Port''' - DAC/ADC interfacing [[BR]] |
| | 30 | |
| | 31 | * '''Control Plane''' - RMAP and RF control [[BR]] |
| | 32 | |
| | 33 | * '''Timing Control''' - system wide clock control using clock enables [[BR]] |
| | 34 | |
| | 35 | From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier classifies and forwards packets according to its |
| | 36 | type : |
| | 37 | * RMAP packets -> RMAP Processor |
| | 38 | * Data packets -> Tx Buffer for APP processing |
| | 39 | * Other packets -> TCP/IP stack |
| | 40 | |
| | 41 | For RMAP read operations, read data must be forwarded back to Host. This is accomplished by following operations : [[BR]] |
| | 42 | 1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.[[BR]] |
| | 43 | 2. Generate IP and Ethernet frame for transmission back to host. Some control header information are added in the payload section for Host RMAP read synchronization.[[BR]][[BR]] |
| | 44 | |
| | 45 | |
