|Version 19 (modified by 12 years ago) ( diff ),|
With R3, the framework design has been modularized such that all modules can be easily replaced or updated without interfering with the overall architecture. This should also improve the migration of block level design into Matlab/Simulink environment.
Furthermore, we have included a dedicated control plane with RMAP processor which will handle all register map related accesses. In future releases, we may replace the RMAP processor with a real 32-bit soft processor such as Xilinx Microblaze, or equivalent processors.
The outline for R3 architecture is as follows :
- Overview - overview of R3 architecture
- Memory Map - system address ranges and register maps
- Packet Format - definition of Ethernet, IPv4 and UDP/TCP headers, also includes packet formats for user specific application
- Control Flow - Message-based control flow (WORK IN PROGRESS)
- Block Level Specs - R3 design module specifications, includes IO specifications. (WORK IN PROGRESS)
- FPGA Architecture - FPGA implementation details. (WORK IN PROGRESS)
- CRKit HW Boot - configuration settings for initial system boot up, includes RF board configurations. (WORK IN PROGRESS)
- CRKit Image - FPGA bit files (WORK IN PROGRESS)