|Version 2 (modified by 13 years ago) ( diff ),|
With R3, the architecture has been modularized such that all modules can be easily replaced or updated without interfering with the overall architecture. This should also improve the migration of block level design into Matlab/Simulink environment.
Furthermore, we have included a dedicated control plane with RMAP processor which will handle all register map related accesses. In future releases, we may replace the RMAP processor with a real 32-bit soft processor such as Xilinx Microblaze, or equivalent processors.