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Jun 15, 2010, 7:30:20 PM (
== R3 Architecture ==
=== Overview ===
With R3, we have included a dedicated control plane with RMAP processor which will handle all register map
related accesses. In future releases, we may replace the RMAP processor with a real 32-bit soft processor such
as Xilinx Microblaze, or equivalent processors.
The register maps associated with the control plane handle all Board related controls e.g. RF SPI, general purpose
IOs, LEDs and so forth. Whereas, data plane centric register maps are maintained within the Tx and Rx data planes.
Within each dataplane, we have an option of having a dataplane top level register map, and/or an application specific
register map. Usually, the top level register map are shared among multiple applications, whereas application
specific register maps are only designed for a particular application.
__Figure 1 - R3 architecture overview__
From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The Tx Command Generator forwards RMAP specific frames to RMAP Processor, whereas data specific frames are routed to the Tx Memory Controller. The RMAP frames are then parsed by the RMAP processor, where a register map read/write operation can be initiated.
For RMAP read operations, the read data need to be forwarded back to Host. This is accomplished by following operations : [[BR]]
1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.[[BR]]
2. Generate Ethernet frame, with added header control information for RMAP read synchronization at Host.[[BR]][[BR]]
=== Global Memory Map ===
R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits19-16 are used for region address decoding between Common control, Receiver and Transmitter as illustrated in figure 3.
__Figure 2 - R3 Global Memory__
'''Common Control''' - Control Plane register map e.g. SPI, LEDs, and board level IO.[[BR]]
'''Common INTC''' - Interrupt Controller map. Individual interrupt lines from Common Control, XMTR and RCVR are consolidated in a single location. Once an interrupt is set (by INTR ethernet frame), Host shall read the INTC status register to identify which of the 3 regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing. [[BR]]
'''XMTR''' - Transmitter register map.[[BR]]
'''RCVR''' - Receiver register map. [[BR]][[BR]]
__Figure 3 - R3 Top Address Decoding__
=== Ethernet Frame Formatting ===
In this section, the ethernet frame payload structures are detailed for Host -> HW, and HW -> Host
directions. Some header information are appended to provide additional control information.[[BR]]
[wiki:Internal/SDR/Firmware/Framework/R3_arch/eth_from_host Host -> HW] : two types of Ethernet frames e.g. rmap and data frames.[[BR]]
[wiki:Internal/SDR/Firmware/Framework/R3_arch/eth_to_host HW -> Host] : two types of Ethernet frames e.g. rmap read and data. The data frames are further classified in additional subtypes such as generic data, FFT data structures and so forth. Host may perform additional processing on the data structures.
Segmentation - this function is performed by the 'Tx Ethernet Interface' module. This module will automatically segment the data structure if size is greater than 1500 bytes (payload is stored in Rx Buffer). Some control information are appended to denote first, intermediate and last segment. Refer to [wiki:Internal/SDR/Firmware/Framework/R3_arch/eth_to_host HW -> Host] for further details.
=== Control Flow ===
As with previous revisions, R3 control flow is message-based. Host sends commands to HW, where they get parsed and acted on accordingly. R3 control flow scheme is detailed in the [wiki:Internal/SDR/Firmware/Framework/R3_arch/ctl_flow Control Flow Diagram].[[BR]][[BR]]
=== Multi-clocks Synchronization ===
=== Block Level Specifications ===
[wiki:Internal/SDR/Firmware/Framework/R3_arch/blk_ctl Control Plane][[BR]]
=== FPGA Architecture ===
The [wiki:Internal/SDR/Firmware/Framework/R3_arch/fpga_arch modularity] of the FPGA architecture design provides a path for upgradeability. All main components can be upgraded or replaced as long as the integrity of IO interfaces are maintained. [[BR]][[BR]]
=== Register Maps ===
[wiki:Internal/SDR/Firmware/Framework Return ..]
Part of ORBIT