Changes between Version 9 and Version 10 of crkit/Software/Firmware/Framework/R3_arch

Timestamp:

Jun 15, 2010, 8:56:50 PM (14 years ago)

Author:

khanhle

Comment:

--

crkit/Software/Firmware/Framework/R3_arch

@@ -32 +32 @@
     
  * '''RF Port''' - DAC/ADC interfacing [[BR]]
+
  * '''Control Plane''' - RMAP and RF control [[BR]]
- * '''Timing Control''' - system wide clock control with clock enables [[BR]]
 
-From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The Tx Command Generator forwards RMAP specific frames to RMAP Processor, whereas data specific frames are routed to the Tx Memory Controller. The RMAP frames are then parsed by the RMAP processor, where a register map read/write operation can be initiated. 
+ * '''Timing Control''' - system wide clock control using clock enables [[BR]]
 
-For RMAP read operations, the read data need to be forwarded back to Host. This is accomplished by following operations : [[BR]]
+From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier forwards RMAP specific frames to RMAP Processor, whereas data specific frames are routed to the Data processing functions. RMAP frames are parsed by the RMAP processor, where a register map read/write operation can be initiated. 
+
+For RMAP read operations, read data are forwarded back to Host. This is accomplished by following operations : [[BR]]
 1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.[[BR]]
-2. Generate Ethernet frame, with added header control information for RMAP read synchronization at Host.[[BR]][[BR]]
+2. Generate IP and Ethernet frame for transmission back to host. Some control header information are added in the 
+payload section for RMAP read synchronization at Host.[[BR]][[BR]]
 
 === Global Memory Map ===