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Changes between Version 12 and Version 13 of crkit/Software/Firmware/Framework/R3_arch


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Timestamp:
Jun 16, 2010, 4:17:54 PM (12 years ago)
Author:
khanhle
Comment:

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  • crkit/Software/Firmware/Framework/R3_arch

    v12 v13  
    5151R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits19-16 are used for region address decoding between Common control, Receiver and Transmitter as illustrated in figure 3.
    5252
    53 __Figure 2 - R3 Global Memory__
    54 [[BR]][[BR]]
    55 [[Image(r3_glob_mem.jpg, 400px)]]
    56 [[BR]][[BR]]
     53__Table 1 - R3 Global Memory Map__
     54||'''Instance'''      ||'''Base Address'''||'''Size'''  ||'''Description'''||
     55||''Reserved''        ||0x00000000-0x0000FFFC||65K      ||Future use||
     56||''Common Control''  ||0x00010000-0x0001FFFC||65K      ||Control Plane register map e.g. SPI, LEDs, and board level IO||
     57||''Common INTC''     ||0x00020000-0x0002FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
     58||''Timing Control''  ||0x00030000-0x0003FFFC||65K      ||address range for timing controller||
     59||''Ethernet Port''   ||0x00040000-0x0004FFFC||65K      ||address range for Tx and Rx Ethernet ports||
     60||''Packet Processor''||0x00050000-0x0005FFFC||65K      ||address range for packet processor||
     61||''Tx APP''          ||0x00060000-0x0006FFFC||65K      ||address range for Tx Application||
     62||''Rx APP''          ||0x00070000-0x0007FFFC||65K      ||address range for Tx Application||
     63||''RF Port - DAC''   ||0x00080000-0x0008FFFC||65K      ||address range for DAC interfacing module||
     64||''RF Port - ADC''   ||0x00090000-0x0009FFFC||65K      ||address range for ADC interfacing module||
     65||''Reserved''        ||0x000A0000-0xFFFFFFFC||-        ||Future use||
     66[[BR]]
    5767
    58 '''Common Control''' - Control Plane register map e.g. SPI, LEDs, and board level IO.[[BR]]
    59 '''Common INTC'''    - Interrupt Controller map. Individual interrupt lines from Common Control, XMTR and RCVR are consolidated in a single location. Once an interrupt is set (by INTR ethernet frame), Host shall read the INTC status register to identify which of the 3 regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing. [[BR]]
    60 '''XMTR'''           - Transmitter register map.[[BR]]
    61 '''RCVR'''           - Receiver register map. [[BR]][[BR]]
    62    
     68 
    6369
    6470__Figure 3 - R3 Top Address Decoding__