Changes between Version 13 and Version 14 of crkit/Software/Firmware/Framework/R3_arch

Timestamp:

Jun 16, 2010, 5:17:18 PM (14 years ago)

Author:

khanhle

Comment:

--

crkit/Software/Firmware/Framework/R3_arch

@@ -49 +49 @@
 === Global Memory Map ===
 
-R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits19-16 are used for region address decoding between Common control, Receiver and Transmitter as illustrated in figure 3. 
+R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits31-28 are used for region address decoding between the individual regions as illustrated in figure 3. 
 
 __Table 1 - R3 Global Memory Map__
 ||'''Instance'''      ||'''Base Address'''||'''Size'''  ||'''Description'''||
-||''Reserved''        ||0x00000000-0x0000FFFC||65K      ||Future use||
-||''Common Control''  ||0x00010000-0x0001FFFC||65K      ||Control Plane register map e.g. SPI, LEDs, and board level IO||
-||''Common INTC''     ||0x00020000-0x0002FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
-||''Timing Control''  ||0x00030000-0x0003FFFC||65K      ||address range for timing controller||
-||''Ethernet Port''   ||0x00040000-0x0004FFFC||65K      ||address range for Tx and Rx Ethernet ports||
-||''Packet Processor''||0x00050000-0x0005FFFC||65K      ||address range for packet processor||
-||''Tx APP''          ||0x00060000-0x0006FFFC||65K      ||address range for Tx Application||
-||''Rx APP''          ||0x00070000-0x0007FFFC||65K      ||address range for Tx Application||
-||''RF Port - DAC''   ||0x00080000-0x0008FFFC||65K      ||address range for DAC interfacing module||
-||''RF Port - ADC''   ||0x00090000-0x0009FFFC||65K      ||address range for ADC interfacing module||
-||''Reserved''        ||0x000A0000-0xFFFFFFFC||-        ||Future use||
+||''Reserved''        ||0x00000000-0x0FFFFFFC||-        ||Future use||
+||''Common Control''  ||0x10000000-0x1000FFFC||65K      ||Control Plane register map e.g. SPI, LEDs, and board level IO||
+||''Common INTC''     ||0x10010000-0x1001FFFC||65K      ||Interrupt Controller map. Individual interrupt lines from all RMAPs are consolidated in a single location. Once an interrupt is set by HW, a status messaging packet is sent to Host. Host shall read the INTC status register to identify which of the RMAP regions has triggered an interrupt e.g. coarse parsing, followed by fine parsing||
+||''Timing Control''  ||0x10020000-0x1002FFFC||65K      ||address range for timing controller||
+||''Ethernet Port''   ||0x10030000-0x1003FFFC||65K      ||address range for Tx and Rx Ethernet ports||
+||''Packet Processor''||0x10040000-0x1004FFFC||65K      ||address range for packet processor||
+||''Tx APP''          ||0x10050000-0x1005FFFC||65K      ||address range for Tx Application||
+||''Rx APP''          ||0x10060000-0x1006FFFC||65K      ||address range for Tx Application||
+||''RF Port - DAC''   ||0x10070000-0x1007FFFC||65K      ||address range for DAC interfacing module||
+||''RF Port - ADC''   ||0x10080000-0x1008FFFC||65K      ||address range for ADC interfacing module||
+||''Reserved''        ||0x10090000-0xFFFFFFFC||-        ||Future use||
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