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- Timestamp:
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Jun 16, 2010, 6:05:41 PM (14 years ago)
- Author:
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khanhle
- Comment:
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v14
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v15
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49 | 49 | === Global Memory Map === |
50 | 50 | |
51 | | R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits31-28 are used for region address decoding between the individual regions as illustrated in figure 3. |
| 51 | R3 global memory map is currently divided into 4 regions : Common control, Common Interrupt Control, Receiver and Transmitter. 65Kbytes are reserved for each region. The total number of address bits are 32-bit, but we will only use the lower 16-bits per region e.g. 65Kbytes per region. Therefore, bits31-28 are used for region address decoding between the individual regions as illustrated in figure 2. |
52 | 52 | |
53 | 53 | __Table 1 - R3 Global Memory Map__ |
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68 | 68 | |
69 | 69 | |
70 | | __Figure 3 - R3 Top Address Decoding__ |
| 70 | __Figure 2 - R3 Top Address Decoding__ |
71 | 71 | [[BR]][[BR]] |
72 | 72 | [[Image(r3_addr_dec.jpg)]] |
73 | 73 | [[BR]][[BR]] |
74 | 74 | |
75 | | === Ethernet Frame Formatting === |
76 | | In this section, the ethernet frame payload structures are detailed for Host -> HW, and HW -> Host |
77 | | directions. Some header information are appended to provide additional control information.[[BR]] |
| 75 | === Packet Formatting === |
| 76 | In this section, the packet structure is detailed. The |
| 77 | |
| 78 | __Figure 3 - Packet Format__ |
| 79 | [[BR]][[BR]] |
| 80 | [[Image(pkt.jpg)]] |
| 81 | [[BR]][[BR]] |
| 82 | |
| 83 | |
| 84 | for Host -> HW, and HW -> Host directions. Some header information are appended to provide additional control information.[[BR]] |
78 | 85 | |
79 | 86 | [wiki:Internal/SDR/Firmware/Framework/R3_arch/eth_from_host Host -> HW] : two types of Ethernet frames e.g. rmap and data frames.[[BR]] |