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- Timestamp:
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Jun 15, 2010, 7:34:53 PM (14 years ago)
- Author:
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khanhle
- Comment:
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17 | 17 | __Figure 1 - R3 architecture overview__ |
18 | 18 | [[BR]][[BR]] |
19 | | [[Image(r3_arch.jpg, 900px)]] |
| 19 | [[Image(r3_arch.jpg, 1200px)]] |
20 | 20 | [[BR]][[BR]] |
21 | 21 | From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The Tx Command Generator forwards RMAP specific frames to RMAP Processor, whereas data specific frames are routed to the Tx Memory Controller. The RMAP frames are then parsed by the RMAP processor, where a register map read/write operation can be initiated. |