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Changes between Version 41 and Version 42 of crkit/Software/Firmware/Framework/R3_arch


Ignore:
Timestamp:
Jun 17, 2010, 8:34:04 PM (14 years ago)
Author:
khanhle
Comment:

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  • crkit/Software/Firmware/Framework/R3_arch

    v41 v42  
    103103   
    104104=== Control Flow ===
     105 WORK IN PROGRESS
    105106As with previous revisions, R3 control flow is message-based. Host sends commands to HW, where they get parsed and acted on accordingly. R3 control flow scheme is detailed in the [wiki:Internal/SDR/Firmware/Framework/R3_arch/ctl_flow Control Flow Diagram].[[BR]][[BR]] 
     107
     108
    106109=== Multi-clocks Synchronization ===
    107 
     110WORK IN PROGRESS
    108111 Elaborate on sync fifo...
    109112
    … …  
    111114
    112115=== Block Level Specifications ===
    113 
     116WORK IN PROGRESS
    114117[wiki:Software/Firmware/Framework/R3_arch/blk_eth Ethernet Port][[BR]]
    115118[wiki:Software/Firmware/Framework/R3_arch/blk_pkt Packet Processor][[BR]]
    … …  
    122125
    123126=== FPGA Architecture ===
    124 
     127WORK IN PROGRESS
    125128The [wiki:Internal/SDR/Firmware/Framework/R3_arch/fpga_arch modularity] of the FPGA architecture design provides a path for upgradeability. All main components can be upgraded or replaced as long as the integrity of IO interfaces are maintained. [[BR]][[BR]]
    126129
    127130=== RMAP/Interrupt Architecture ===
    128 
     131WORK IN PROGRESS
    129132[[BR]][[BR]]
    130133 
    131 === Register Maps ===
    132 [[BR]][[BR]] 
    133134
    134135[..]