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- Timestamp:
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Jun 17, 2010, 8:34:04 PM (14 years ago)
- Author:
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khanhle
- Comment:
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--
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v41
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v42
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103 | 103 | |
104 | 104 | === Control Flow === |
| 105 | WORK IN PROGRESS |
105 | 106 | As with previous revisions, R3 control flow is message-based. Host sends commands to HW, where they get parsed and acted on accordingly. R3 control flow scheme is detailed in the [wiki:Internal/SDR/Firmware/Framework/R3_arch/ctl_flow Control Flow Diagram].[[BR]][[BR]] |
| 107 | |
| 108 | |
106 | 109 | === Multi-clocks Synchronization === |
107 | | |
| 110 | WORK IN PROGRESS |
108 | 111 | Elaborate on sync fifo... |
109 | 112 | |
… |
… |
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111 | 114 | |
112 | 115 | === Block Level Specifications === |
113 | | |
| 116 | WORK IN PROGRESS |
114 | 117 | [wiki:Software/Firmware/Framework/R3_arch/blk_eth Ethernet Port][[BR]] |
115 | 118 | [wiki:Software/Firmware/Framework/R3_arch/blk_pkt Packet Processor][[BR]] |
… |
… |
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122 | 125 | |
123 | 126 | === FPGA Architecture === |
124 | | |
| 127 | WORK IN PROGRESS |
125 | 128 | The [wiki:Internal/SDR/Firmware/Framework/R3_arch/fpga_arch modularity] of the FPGA architecture design provides a path for upgradeability. All main components can be upgraded or replaced as long as the integrity of IO interfaces are maintained. [[BR]][[BR]] |
126 | 129 | |
127 | 130 | === RMAP/Interrupt Architecture === |
128 | | |
| 131 | WORK IN PROGRESS |
129 | 132 | [[BR]][[BR]] |
130 | 133 | |
131 | | === Register Maps === |
132 | | [[BR]][[BR]] |
133 | 134 | |
134 | 135 | [..] |