Changes between Version 42 and Version 43 of crkit/Software/Firmware/Framework/R3_arch
- Timestamp:
- Jun 17, 2010, 8:34:47 PM (14 years ago)
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crkit/Software/Firmware/Framework/R3_arch
v42 v43 103 103 104 104 === Control Flow === 105 WORK IN PROGRESS 105 WORK IN PROGRESS[[BR]] 106 106 As with previous revisions, R3 control flow is message-based. Host sends commands to HW, where they get parsed and acted on accordingly. R3 control flow scheme is detailed in the [wiki:Internal/SDR/Firmware/Framework/R3_arch/ctl_flow Control Flow Diagram].[[BR]][[BR]] 107 107 108 108 109 109 === Multi-clocks Synchronization === 110 WORK IN PROGRESS 110 WORK IN PROGRESS[[BR]] 111 111 Elaborate on sync fifo... 112 112 … … 114 114 115 115 === Block Level Specifications === 116 WORK IN PROGRESS 116 WORK IN PROGRESS[[BR]] 117 117 [wiki:Software/Firmware/Framework/R3_arch/blk_eth Ethernet Port][[BR]] 118 118 [wiki:Software/Firmware/Framework/R3_arch/blk_pkt Packet Processor][[BR]] … … 125 125 126 126 === FPGA Architecture === 127 WORK IN PROGRESS 127 WORK IN PROGRESS[[BR]] 128 128 The [wiki:Internal/SDR/Firmware/Framework/R3_arch/fpga_arch modularity] of the FPGA architecture design provides a path for upgradeability. All main components can be upgraded or replaced as long as the integrity of IO interfaces are maintained. [[BR]][[BR]] 129 129 130 130 === RMAP/Interrupt Architecture === 131 WORK IN PROGRESS 131 WORK IN PROGRESS[[BR]] 132 132 [[BR]][[BR]] 133 133