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Changes between Version 42 and Version 43 of crkit/Software/Firmware/Framework/R3_arch


Ignore:
Timestamp:
Jun 17, 2010, 8:34:47 PM (12 years ago)
Author:
khanhle
Comment:

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  • crkit/Software/Firmware/Framework/R3_arch

    v42 v43  
    103103   
    104104=== Control Flow ===
    105  WORK IN PROGRESS
     105 WORK IN PROGRESS[[BR]]
    106106As with previous revisions, R3 control flow is message-based. Host sends commands to HW, where they get parsed and acted on accordingly. R3 control flow scheme is detailed in the [wiki:Internal/SDR/Firmware/Framework/R3_arch/ctl_flow Control Flow Diagram].[[BR]][[BR]] 
    107107
    108108
    109109=== Multi-clocks Synchronization ===
    110 WORK IN PROGRESS
     110WORK IN PROGRESS[[BR]]
    111111 Elaborate on sync fifo...
    112112
     
    114114
    115115=== Block Level Specifications ===
    116 WORK IN PROGRESS
     116WORK IN PROGRESS[[BR]]
    117117[wiki:Software/Firmware/Framework/R3_arch/blk_eth Ethernet Port][[BR]]
    118118[wiki:Software/Firmware/Framework/R3_arch/blk_pkt Packet Processor][[BR]]
     
    125125
    126126=== FPGA Architecture ===
    127 WORK IN PROGRESS
     127WORK IN PROGRESS[[BR]]
    128128The [wiki:Internal/SDR/Firmware/Framework/R3_arch/fpga_arch modularity] of the FPGA architecture design provides a path for upgradeability. All main components can be upgraded or replaced as long as the integrity of IO interfaces are maintained. [[BR]][[BR]]
    129129
    130130=== RMAP/Interrupt Architecture ===
    131 WORK IN PROGRESS
     131WORK IN PROGRESS[[BR]]
    132132[[BR]][[BR]]
    133133