== Build Simulink App == The CRKit subsystem is as shown in Figure 1. We have three subsystems : 1. '''TB PKT SUB''' - testbench for Ethernet and IP level processing 2. '''APP SUB''' - User Specific Application module. This module is the one which will be built, and ported to external Xilinx ISE tool for further framework integration 3. '''TB RF SUB''' - testbench for RF interface. Currently a simple loop interface between dac and adc interfaces e.g. Tx DAC -> Rx ADC __Figure 1 - CRKit Subsystem__ [[BR]][[BR]] [[Image(crkit_sub.png, 1300px)]] [[BR]][[BR]] The APP subsystem is shown in Figure 2. This module will be built using System Generator (double-click on System Generator icon). __Figure 2 - APP Subsystem__ [[BR]][[BR]] [[Image(app_sub.png, 1300px)]] [[BR]][[BR]] The system generator options are shown in Figure 3. Assuming that the Application module has passed the verification/simulation stages successfully, you may build the APP module by clicking on 'Generate'. Note the target directory is `d:\hw\simulink\ngc_netlist`, and the clock rate is set to 100MHz. Once the build process is completed, we should have a '''app_sub.ngc''' file which is the synthesized version of '''APP subsystem'''. Now, copy '''app_sub.ngc''' to Xilinx ISE CRKit project folder e.g. `d:\hw\cr_build\cr_r3_sim` . We are now ready to link '''app_sub.ngc''' to the framework using Xilinx ISE tool. __Figure 3 - System Generator__ [[BR]][[BR]] [[Image(sysgen.png, 400px)]] [[BR]][[BR]] [..]