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- Timestamp:
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Nov 17, 2010, 6:40:23 PM (13 years ago)
- Author:
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khanhle
- Comment:
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v12
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v13
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12 | 12 | [[BR]][[BR]] |
13 | 13 | |
14 | | 3. You have the option to re-synthesize the framework. Note the application module e.g. app_sub.ngc is not synthesized at this stage, this has been done within MATLAB/Simulink. To synthesize the framework, right-click on '''Synthesize - XST''' in processes window, and select run or re-run. This step can be skipped if you already have synthesize the framework at an earlier stage, hence save some build time. [[BR]][[BR]] |
| 14 | 3. You have the option to re-synthesize the framework. Note the application module e.g. app_sub.ngc is not synthesized at this stage, this has been done within MATLAB/Simulink. To synthesize the framework, right-click on '''Synthesize - XST''' in processes window, and select run or re-run. This step can be skipped if you already have synthesized the framework at an earlier stage, hence save some build time. [[BR]][[BR]] |
15 | 15 | 4. Proceed with the place/route stage. Right-click on '''Implement Design''' in processes window, and select run or re-run. Once this step is completed succesfully, you should see '''All Signals Completely Routed''' and '''All Constraints Met''' under the project status as shown in Figure 2. [[BR]][[BR]] |
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20 | 20 | [[BR]][[BR]] |
21 | 21 | |
22 | | 5. Generate bit file. Right-click on 'Generate Programming File' in processes window, and select run or re-run. Once this step is done, the bit file is available at d:\hw\cr_build\cr_r3_sim\'''cr_top.bit''' . |
| 22 | 5. Generate bit file. Right-click on 'Generate Programming File' in processes window, and select run or re-run. Once this step is done, the bit file is available at d:\hw\cr_build\cr_r3_sim\'''cr_top.bit''' . [[BR]] |
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| 24 | 6. Use Xilinx Impact tool to download the bit file onto the FPGA. [[BR]] |
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| 26 | 7. FPGA is ready to transmit/receive Ehernet packets to/from host. |
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23 | 29 | |