close Warning: Can't synchronize with repository "(default)" (/common/SVN/crkit does not appear to be a Subversion repository.). Look in the Trac log for more information.

Version 18 (modified by khanhle, 12 years ago) ( diff )


Build Framework

Once app_sub.ngc has been copied to current ISE project folder, we are now ready to build the framework and generate a bit file for FPGA download.

Perform following operations :

  1. Start Xilinx ISE

  2. Open CRKit project located at d:\hw\cr_build\cr_r3_sim\'''cr_r3.ise''' . The opened project should look like as shown in Figure 1.

Figure 1 - ISE cr_r3 project

  1. You have the option to re-synthesize the framework. Note the application module e.g. app_sub.ngc is not synthesized at this stage, this has been done within MATLAB/Simulink. To synthesize the framework, right-click on Synthesize - XST in processes window, and select run or re-run. This step can be skipped if you already have synthesized the framework at an earlier stage, hence save some build time.

  2. Proceed with the place/route stage. Right-click on Implement Design in processes window, and select run or re-run. Once this step is completed succesfully, you should see All Signals Completely Routed and All Constraints Met under the project status as shown in Figure 2.

Figure 2 - Project Status

  1. Generate bit file. Right-click on 'Generate Programming File' in processes window, and select run or re-run. Once this step is done, the bit file is available at d:\hw\cr_build\cr_r3_sim\'''cr_top.bit''' .
  1. Use Xilinx Impact tool to download the bit file onto the FPGA.
  1. FPGA is ready to transmit/receive Ehernet packets to/from host. Use your own host software application to do so. However, we do have a Visual Studio based software available on CRKit svn.


Attachments (2)

Download all attachments as: .zip

Note: See TracWiki for help on using the wiki.