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- Timestamp:
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Aug 3, 2010, 3:39:32 PM (13 years ago)
- Author:
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khanhle
- Comment:
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v3
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v4
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8 | 8 | Note : Bluespec is a higher level design language than RTL. They claim |
9 | 9 | we can speed up the design and verification processes by 50%. |
10 | | 3. migrate to Verilog/Systemverilog (?) |
| 10 | 3. migrate to Verilog/Systemverilog |
11 | 11 | 4. include a complete transceiver design e.g. OFDM based, and so forth... |
12 | 12 | 5. PCIe support |