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Version 2 (modified by khanhle, 12 years ago) ( diff )



Ongoing work in the following areas :

Firmware :

  1. Multi-clock domain synchronization e.g. adc -> sys_clk, sys_clk -> dac, eth <-> sys_clk. Will need clock enable capability support.
  2. Add RMAP read ability (send ethernet frame with a RMAP read request, the response will be an ethernet going back to host)
  3. Redesign RMAP to work with both ISE and MATLAB.
  4. Add 1Gbps Ethernet support
  5. Add data frame segmentation ability for ethernet packets. Rx data may be larger than Ethernet frame size. Therefore, we will need to segment the data into multiple ethernet frames
  6. Integrate Rx chain into MATLAB/Simulink environment
  7. Update current build_fw, syn_fw and par_fw scripts to support dynamically allocated application modules
  8. Revisit current SVN folder structure to support multiple apps
  9. Add modulator into Tx use apps e.g. muxing between SINE, AWGN and host data
  10. Documentation : wiki, tutorials
  11. Add support for Freebo and WDR e.g. RMAP, SPI read capabilities

Software :


R2 -> R3 : required changes to R2 revision for migration to R3.


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