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Changes between Version 4 and Version 5 of wiser/gFPGA


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Timestamp:
Aug 1, 2014, 5:23:25 AM (9 years ago)
Author:
prasanthi
Comment:

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  • wiser/gFPGA

    v4 v5  
    77[[Image(fig01_dyn_app.png, 400px)]]
    88
    9 FPGA framework architecture for Zynq based platforms is shown below.
     9FPGA framework architecture for Zynq based platforms is as shown below. Main blocks of the framework are
     101) Processor subsystem - Signle ARM Cortex A9 core is being used with dual AXI bus architecture, AXI0 for Ehternet/IP packet traffic, and AXI1 for all the other data such as hardware configuration, system control and monitoring.
     112) Ethernet processing - provides Ethernet packing/unpacking functionality, and integrating with A
     12 
    1013
    1114[[Image(fig01_framework.png, 500px)]]