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Changes between Version 5 and Version 6 of wiser/gFPGA


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Timestamp:
Aug 1, 2014, 5:29:42 AM (6 years ago)
Author:
prasanthi
Comment:

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  • wiser/gFPGA

    v5 v6  
    99FPGA framework architecture for Zynq based platforms is as shown below. Main blocks of the framework are
    10101) Processor subsystem - Signle ARM Cortex A9 core is being used with dual AXI bus architecture, AXI0 for Ehternet/IP packet traffic, and AXI1 for all the other data such as hardware configuration, system control and monitoring.
    11 2) Ethernet processing - provides Ethernet packing/unpacking functionality, and integrating with A
     112) Ethernet processing - provides Ethernet packing/unpacking functionality, and integration with AXI bus architecture. Since GigE MAC resides within the embedded CPU sub-system, DMA is therefore is used to transfer incoming and outgoing traffic between Framework and GbE MAC module. Note that the processor is not invoked for this type of data transfers; it is only used to setup the DMA transaction descriptors.
     123) Packet Processor - simple packet classification/forwarding scheme based on IP/UDP. Control packets get routed to the processor core, where as data packets are forwarded to corresponding APP for further wireless layer processing. It supports a subset of VITA Radio Transport protocol.
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