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Changes between Version 6 and Version 7 of wiser/gFPGA


Ignore:
Timestamp:
Aug 1, 2014, 5:33:33 AM (9 years ago)
Author:
prasanthi
Comment:

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  • wiser/gFPGA

    v6 v7  
    11112) Ethernet processing - provides Ethernet packing/unpacking functionality, and integration with AXI bus architecture. Since GigE MAC resides within the embedded CPU sub-system, DMA is therefore is used to transfer incoming and outgoing traffic between Framework and GbE MAC module. Note that the processor is not invoked for this type of data transfers; it is only used to setup the DMA transaction descriptors.
    12123) Packet Processor - simple packet classification/forwarding scheme based on IP/UDP. Control packets get routed to the processor core, where as data packets are forwarded to corresponding APP for further wireless layer processing. It supports a subset of VITA Radio Transport protocol.
     134)RMAP Processor - general sub-system interfacing and control, provides processor interfacing and address decoding.
     145)APP design space - integrates two presumably orthogonal design spaces into a full working system.
    1315 
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