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- Timestamp:
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Jul 20, 2010, 3:18:43 PM (14 years ago)
- Author:
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khanhle
- Comment:
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5 | 5 | 1. Set up the build environment as explained in "How to setup build environment" tutorial. |
6 | | 1. Create a top level VHDL file of your design from within MATLAB (if using the provided Simulink CRKit Framework, then the top Input/Output (IO) signals should match the IOs of the testbench environment). |
7 | | 2. Port top file into the external testbench environment |
| 6 | 2. Create a top level VHDL file of your design from within MATLAB (if using the provided Simulink CRKit Framework, then the top Input/Output (IO) signals should match the IOs within the testbench environment). |
| 7 | 3. Port top file into the external testbench environment |
| 8 | 4. Build the simulation testbench by either using the currently available testcases, or create your own test scenarios. |
| 9 | 5. Validate your design in Modelsim. |
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