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- Timestamp:
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Jun 15, 2010, 6:44:50 PM (14 years ago)
- Author:
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khanhle
- Comment:
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v1
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| 1 | == R3 == |
| 2 | |
| 3 | Ongoing work in the following areas : |
| 4 | |
| 5 | Firmware : |
| 6 | 1. Multi-clock domain synchronization e.g. adc -> sys_clk, sys_clk -> dac, eth <-> sys_clk. Will need clock enable capability support. |
| 7 | 2. Add RMAP read ability (send ethernet frame with a RMAP read request, the response will be an ethernet going back to host) |
| 8 | 3. Redesign RMAP to work with both ISE and MATLAB. |
| 9 | 4. Add 1Gbps Ethernet support |
| 10 | 5. Add data frame segmentation ability for ethernet packets. Rx data may be larger than Ethernet frame size. Therefore, we will need |
| 11 | to segment the data into multiple ethernet frames |
| 12 | 6. Integrate Rx chain into MATLAB/Simulink environment |
| 13 | 7. Update current build_fw, syn_fw and par_fw scripts to support dynamically allocated application modules |
| 14 | 8. Revisit current SVN folder structure to support multiple apps |
| 15 | 9. Add modulator into Tx use apps e.g. muxing between SINE, AWGN and host data |
| 16 | 10. Documentation : wiki, tutorials |
| 17 | 11. Add support for Freebo and WDR e.g. RMAP, SPI read capabilities |
| 18 | |
| 19 | Software : |
| 20 | 1. ADD CONTENT |
| 21 | |
| 22 | [wiki:Software/Firmware/ProjectPlanning/R3/R2toR3 R2 -> R3] : required changes to R2 revision for migration to R3. [[BR]] |
| 23 | |
| 24 | [wiki:Software/Firmware/ProjectPlanning Return ..] |