|Version 1 (modified by 12 years ago) ( diff ),|
Ongoing work in the following areas :
- Multi-clock domain synchronization e.g. adc -> sys_clk, sys_clk -> dac, eth <-> sys_clk. Will need clock enable capability support.
- Add RMAP read ability (send ethernet frame with a RMAP read request, the response will be an ethernet going back to host)
- Redesign RMAP to work with both ISE and MATLAB.
- Add 1Gbps Ethernet support
- Add data frame segmentation ability for ethernet packets. Rx data may be larger than Ethernet frame size. Therefore, we will need to segment the data into multiple ethernet frames
- Integrate Rx chain into MATLAB/Simulink environment
- Update current build_fw, syn_fw and par_fw scripts to support dynamically allocated application modules
- Revisit current SVN folder structure to support multiple apps
- Add modulator into Tx use apps e.g. muxing between SINE, AWGN and host data
- Documentation : wiki, tutorials
- Add support for Freebo and WDR e.g. RMAP, SPI read capabilities
- ADD CONTENT
R2 -> R3 : required changes to R2 revision for migration to R3.
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